1. Technical Field
The present invention relates to a technology for generating a clock signal having a 50% duty cycle, and more particularly to a duty cycle tuning circuit and a method thereof.
2. Related Art
In many high-speed and high-performance applications, it is required to provide a clock signal having a 50% duty cycle to a system. For example, in a double data rate synchronous dynamic random-access memory (DDR SDRAM) system, a rising edge and a falling edge of a clock signal are used to process data to achieve an objective that the data transmission rate is increased by 100% in the same clock frequency. In this application, the clock signal must have a precise 50% duty cycle; otherwise, timing margin in the data processing is decreased and then the data transmission rate is reduced.
In an ordinary tuning circuit, two delay chains are used to tune the rising edge and the falling edge of the clock signal to make the signal have a 50% duty cycle. However, in this tuning mode, it is difficult to provide a great tuning range (for example, over 10% of the clock cycle of the clock signal). Although the tuning mode may provide a high tuning precision (for example, 1 ps/step), the application range and the output precision of the tuning circuit are limited.
That is, in the tuning method, the delay tuning completely depends on the delay chain. Therefore, the tuning circuit must have a capability of tuning a clock cycle of over ±10%; that is, it is required that the delay tuning range of the delay chain should be greater than 20% of the clock cycle. Taking the DDR SDRAM system for example, to meet the requirements, the delay tuning range of the delay chain is approximately hundreds of picoseconds (ps). Since the delay chain itself has a proportion of fixed delay, an additional part of fixed delay is added when the requirements of the tuning range is met. For example, if the tuning range of the delay chain is from 600 ps to 1 nanosecond (ns), a fixed delay of 600 ps is added to the delay chain itself, when a variable delay of 400 ps is performed on the delay chain. However, an excessively great additional delay is generally not desired in many applications. In addition, since the delay chain itself is significantly affected by external factors (such as, temperature, voltage, and process drift), the delay variation may be two to three times. To meet the requirements of the tuning range in any case, it is required that the maximum delay of the delay chain should be usually over-designed to more than two times of the required tuning range. In this case, the problem of the additional delay of the tuning circuit becomes more serious, and the area and the power consumption of the tuning circuit are also increased. In another aspect, to reach a higher tuning precision, it is required that the tuning resolution of the delay chain should be set to a very small value, for example, 1 ps/step (1 ps is delayed per step). In the case of the great tuning range and the high tuning precision, a great number of unit delay cells are needed, so that the complexity of the tuning circuit is increased significantly, it is also difficult to control the influence of the parasitic effect, and furthermore, the area and the power consumption of the tuning circuit are increased.